The present invention relates to a semiconductor device, especially relates to a semiconductor device using a gallium nitride (GaN)-based semiconductor.
With increasing the importance of electric energy to realize energy saving society, in the twenty first-century, it is going to rely on electric power further. The key devices of electric and electronic equipments are semiconductor devices such as transistors or diodes, etc. Therefore, energy saving characteristic of these semiconductor devices is very important. At present, a power conversion device is a silicon (Si) semiconductor device, but the silicon semiconductor device has been improved its performance to the limit of physical properties, therefore, it is under difficult situation to save energy further.
For this, the research and development has been carried out intensively on the power conversion devices with a wide-gap semiconductor such as silicon carbide (SiC), and gallium nitride (GaN), etc. in place of Si. Among them, GaN has remarkably better physical properties in power efficiency and voltage-resistance property than SiC, therefore, the research and development for GaN-based semiconductor devices has been carried out energetically.
With regard to the GaN-based semiconductor device, a horizontal type device of a field effect transistor (FET) type, that is, a device with a structure formed with a transporting channel parallel to a substrate has been developed. For example, a device wherein upon a base substrate made of sapphire or SiC, etc., an undoped GaN layer is stacked with a few-μm-thick, and on it, an AlGaN layer of which Al composition is about 25% is stacked with about from 25 to 30-nm-thick, and makes use a two-dimensional electron gas (2DEG) generating at an AlGaN/GaN hetero-interface. The device is generally called a HFET (hetero-junction FET).
The AlGaN/GaN HFET has a technical problem of control of current collapse. The phenomenon of current collapse is a phenomenon when high voltage of several hundred voltages is applied between a source and a drain, the drain current value decreases. The current collapse is not a unique phenomenon in a GaN-based FET, but comes to appear remarkably with enabling to apply high voltage between a source and a drain by the GaN-based FET, and is originally a phenomenon generally arising in horizontal type devices.
The cause of generation of current collapse is explained as follows. When a high voltage is applied between a gate and a drain of a FET, or between a cathode and an anode of a diode, a high electric field area is generated just below the gate or just below the anode, but electrons transfer to the surface or surface vicinity of a part of the high electric field, and are trapped. The source of electrons is electrons which drift on the surface of a semiconductor from a gate electrode, or channel electrons which transfer to the surface with high electric field, etc. By being biased to negative by the negative charges of the electrons, the electron density of the electronic channel decreases and the channel resistance goes up.
With regard to electrons generated by gate leakage, by making passivation by the dielectric film on the surface, electron transfer is limited and the current collapse is controlled. However, current collapse cannot be controlled only by the dielectric film.
Therefore, focusing on that the current collapse results from high electric field in the vicinity of a gate, a technique to control the intensity of electric field strength, especially peak electric field, has been developed. This is called the Field Plate (FP) technique, which is the heretofore known technique already in practical use in a Si-based or a GaAs-based FET (for example, see NPL 1.).
FIG. 1A shows a conventional AlGaN/GaN HFET using the field plate technique. As shown in FIG. 1A, with regard to the AlGaN/GaN HFET, on a base substrate 81, a GaN layer 82 and an AlGaN layer 83 are sequentially stacked, and on the AlGaN layer 83, a gate electrode 84, a source electrode 85, and a drain electrode 86 are formed. In this case, the upper part of the gate electrode 84 and the upper part of the source electrode 85 extend to the side of the drain electrode 86 like a hat brim, and form a field plate. By the field plates formed to the gate electrodes 84 and the source electrode 85, based on the electromagnetic theory, the peak electric field intensity of the end of a depletion layer of a channel can be lowered. FIG. 1B shows the electric field distribution of with and without a field plate. As the area of electric field distribution is equal to a drain voltage, by dispersing the peak electric field, the improvement of voltage resistance of the AlGaN/GaN HFET and a control of current collapse can be made.
However, by the field plate technique, the electric field cannot be leveled over all the channel area. Also, a practical semiconductor device as a power device is applied a voltage of 600 V or more, therefore, the issue does not be fundamentally resolved even if the field plate technique is applied.
On the other hand, there is a super junction structure, one of the heretofore known technique, which improves voltage resistance by equalizing the electric field distribution, and making the peak electric field unlikely occur (for example, see NPL 2.). The super junction is explained.
FIG. 2A shows a conventional pn junction applied a small reverse-bias voltage. FIG. 3A shows a unit of a super junction applied a small reverse-bias voltage.
As shown in FIG. 2A, in the conventional pn junction, a p-type layer 101 and an n-type layer 102 are joined, a p-electrode 103 is formed on the p-type layer 101, and an n-electrode 104 is formed on the n-type layer 102, and the junction plane of the pn junction is parallel to the p-electrode 103 and the n-electrode 104. In the vicinity part of the junction plane of the p-type layer 101, a depletion layer 101a is formed, and the other part is a p-type neutral region. On the vicinity part of the junction plane of the n-type layer 102, a depletion layer 102a is formed, and the other part is an n-type neutral region.
For this, as shown in FIG. 3A, in the super junction, which is the same as the conventional pn junction in forming a pn junction by a p-type layer 201 and an n-type layer 202, but a p-electrode 203 formed on the p-type layer 201 and an n-electrode 204 formed on the n-type layer 202 are formed by intersecting at right angle for the main junction plane stretching in a plane between the p-type layer 201 and the n-type layer 202. At the both end parts of the pn junction, the junction plane is curved to the opposite direction each other for the main junction plane. In the vicinity part of the junction plane of the p-type layer 201, a depletion layer 201a is formed, and the other part is a p-type neutral region. In the vicinity part of the junction plane of the n-type layer 202, a depletion layer 202a is formed, and the other part is an n-type neutral region.
FIG. 2B shows the electric field distribution of a conventional pn junction applied a small reverse bias voltage between the p-electrode 103 and the n-electrode 104 corresponding to FIG. 2A. Also, FIG. 3B shows the electric field distribution of the super junction applied a small reverse bias voltage between the p-electrode 203 and the n-electrode 204 corresponding to FIG. 3A.
FIG. 4A shows that a large reverse bias voltage is applied to a conventional pn junction. FIG. 5A shows that a large reverse bias voltage is applied to the super junction.
FIG. 4B shows the electric field distribution of a conventional pn junction applied a large reverse bias voltage between the p-electrode 103 and the n-electrode 104 corresponding to FIG. 4A. Also, FIG. 5B shows the electric field distribution of the super junction applied a large reverse bias voltage between the p-electrode 203 and the n-electrode 204 corresponding to FIG. 5A.
The expansion of the depletion layers 101a, 102a, 201a, and 202a occurs starting at the pn junction surface, which is the same as the conventional pn junction and the super junction. In the conventional pn junction, the electric field distribution by fixed charges of acceptor ions and donor ions, etc. in the depletion layers 101a and 102a becomes triangle shape as shown in FIG. 2B and FIG. 4B, and the peak electric field distribution occurs. For this, in the super junction, as shown in FIG. 3B and FIG. 5B, when the depletion layers 201a and 202a expand, the electric field (value of integral of charges) distributes at constant value in the direction connecting between the p-electrode 203 and the n-electrode 204, and it is known that concentration of electric field does not occur.
As the applied voltage is the value of integral of electric field (in the FIG. 2B, FIG. 3B, FIG. 4B and FIG. 5B, corresponding to electric field area), in the conventional pn junction, the voltage resistance is controlled by the maximum electric field intensity occurring at the junction plane. On the other hand, the super junction can withstand the applied voltage over whole semiconductor with homogeneous electric field. The super junction is applied in a drift layer of a Si-MOS power transistor and a Si power diode having a vertical type and a horizontal type structure.
Also, there is a theory of polarization junction as a method to cause distribution of positive charges and negative charges as the same as the super junction without depending on the pn junction (for example, see PTL 1.). Also, there is proposed a technique aiming high voltage resistance by making use of the polarization (for example, see PTL 2.).